There are many different ways of doing conditional execution. For some processing architectures, the condition determines whether an operation is executed. For other processing architectures, alternative operations are executed and the condition determines which result is used. The amount of conditional operations that can be performed is limited by the number of predicate registers available to store each condition and also opcode (encoding) limits.
As an example, the C64x processor core has six predicate registers and the C62x processor core has five predicate registers. The predicate register used for a particular instruction is signaled by bits 31-29 of the opcode space (the “creg” field). The sense of the predication is signaled by bit 28 of the opcode space (the “z” field). The predication values for the opcode space of the C64x and C62x processor cores is shown in Table 1.
TABLE 1Predication valueCREG valueSense valueUnconditional000 0(z)Software Breakpoints000 1(z)B00010/1(z)B10100/1(z)B20110/1(z)A11000/1(z)A21010/1(z)A01100/1(z)Compact Instructions111 0(z)
The only unused opcode space for the C64x and C62x processor cores is creg=111 and z=1. However, this unused opcode space is not even adequate to specify one predicate register since both values of the sense bit are not available. As applications become more complicated, availability of additional predicate registers would improve processing efficiency of the C64x and C62x processor cores or other processing architectures. However, changing the opcode space is not a viable option for processing architectures already in use.